In system LSIs used for a gizmo (personal digital assistant (PDA), hand-held device) typically represented by mobile telephones, there has been an increasing demand for long time operation by a battery of restricted capacity. Particularly, in a mobile telephone, it is extremely important to reduce the power consumption during a long waiting time (a state in which the power source is turned on, but processing under high load is not conducted) in order to satisfy the requirement for long time operation. One of the methods includes stopping all clocks of the system LSI in the standby mode (referred to as a software standby state which is called a standby mode with gating of the system clock distribution). In the software standby state, since clocks in the system LSI are stopped upon entering the standby mode, the consumption of current by the circuit operation in the system LSI is reduced to substantially zero. Accordingly, the standby current in the standby mode consists only of the consumption of current due to leakage current.
However, in a case of using an insulated gate type field effect transistor using a modern fine process (in the present application, the insulated gate type field effect transistor is referred to as a MISFET), various kinds of leakage current are extremely large, being typically represented by a subthreshold leakage current caused by lowering of the threshold voltage of transistors in accordance with the voltage lowering of the power voltage or gate tunneling leakage current caused by reduction of the thickness of the gate insulation film in a MISFET. Since the standby current consumes power, a long waiting time cannot be attained.
With the situations described above, a method for effecting shut down of the power for the system LSI during the standby mode (referred to as the U-standby mode) has been proposed by T. Yamada, et al., “A 133 MHz 170 mW 10 μA Standby Application Processor for 3G Cellular Phones”. ISSCC 2002, February, pp. 370-371 (Non-Patent Document 1). In the U-standby mode, the supply of power is shut down except for circuits of a minimal number required for returning when it enters into the waiting state. As a result, not only the consumption of current by the circuit operation, but also the consumption of current due to leakage current are reduced substantially to zero, and the standby current can be reduced to substantially zero.
Then, when both of them are compared in view of the returning time from the standby mode, they are as described below. At first, in the software standby state, since the internal status of the system LSI (such as a register value) can be retained also in the standby mode, it is possible to return from the standby mode by interruption. Accordingly, the time required for returning is about equal to the time necessary for restarting the clocks, and so it can be returned at high speed. On the contrary, in the U-standby mode, since the internal status of the system LSI is destroyed by the power shutdown, it cannot be returned from the standby mode only by interruption, and so resetting is necessary for the return to operation. The resetting includes booting of the software necessary for the initialization and operation of the system LSI and needs a long time. Since software booting needs a number of instructions to be conducted, the processing time is particularly long. In a the case of returning from the U-standby mode, the interruption is not conducted for the interruption request as it is, but resetting is first applied and then processing corresponding to the interruption request is conducted after booting of the software.
Further, as disclosed in S. Mutoh, et al., “A 1 V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application, ISSCC 1996, February, pp. 168-169 (Non-Patent Document 2), and V. Zyuban, et al., “Low Power Integrates Scan-Retention Mechanism”, ISLPED 2002, August, pp. 98-102 (Non-Patent Document 3), it has been proposed to supply power to a portion of the data retention circuits in the circuit block under power shutdown in the standby mode to retain the data also in the standby mode. Specifically, a latch circuit supplied with power even in a standby mode is disposed to the flip-flop in the circuit block and it operates to retain the internal data also during power shutdown by the latch circuit, thereby enabling a return to the original state at high speed.